1. Field of the Invention
The invention pertains to a semiconductor memory, and more particularly, to a nonvolatile ferroelectric memory device and a method for storing a multiple bit using the same.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to that of a dynamic random access memory (DRAM) and retains data even when the power is off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices having similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 illustrates a hysteresis loop of a related art general ferroelectric. As shown in FIG. 1, even if polarization is induced by the electric field and the electric field is removed, data is maintained at a certain level (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory is described with reference to the accompanying drawings.
FIG. 2 is a schematic diagram of a unit cell of a related art general nonvolatile ferroelectric memory device.
As shown in FIG. 2, the nonvolatile ferroelectric memory device includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 having a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with the drain of the transistor T1 and a second terminal is connected with the plate line P/L.
Data input/output operation of the above-mentioned nonvolatile ferroelectric memory device is described below.
FIG. 3A illustrates a timing diagram of a write mode operation of the related art nonvolatile ferroelectric memory device, and FIG. 3B illustrates a timing diagram of a read mode operation of the related art nonvolatile ferroelectric memory device.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. When a low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
The reading operation of data stored in a cell is described below.
If an externally applied chip enable signal CSBpad is activated from high state to low state, all of the bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data Qs corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data Qs are not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited to an “f” state as shown in hysteresis loop of FIG. 1.1. If the data is not destroyed, “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in the case that the data is destroyed while the logic value “0” is output in the case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state in a state that the high signal is applied to the corresponding wordline. In the aforementioned nonvolatile ferroelectric memory device, data logic “1” or “0” is written in one cell.
The above-mentioned related art nonvolatile ferroelectric memory device has a problem in that since the data of logic “1” or “0” is written, it is difficult to reduce the layout area. That is, the related art fails to allow multiple conventional memory cells to be replaced with one memory cell. Therefore, reductions in chip size and the price competitiveness of the chip are not easily obtained through the related art technology.